Boundary scan test, test methodology, and fault modeling

An Embedded Boundary Scan Test System

This paper describes an application of boundary scan IEEE Std. 1149.1 at system level. It provides the description of the design and the implementation options of a VME boundary scan controller board prototype and the corresponding software. The prototype was designed to use the Module Test and Maintenance (MTM) bus, existing in the VME 64x backplane, to apply the IEEE 1149.1 test vectors to a ...

System issues in boundary-scan board test

Boards have evolved into complex systems and even collections of interacting systems. Test engineers struggle to find out how these systems are initialized and booted because of poor documentation. While Boundary-Scan (IEEE Std 1149.1) [IEEE93, Park98] is a powerful test tool, test engineers are finding out that yesterday's DFT rules and test approaches may actually be detrimental to successful...

A Roadmap for Boundary-Scan Test Reuse

This paper proposes a Layered Model for boundaryscan testing to help identify opportunities for standardization. Serial Vector Format [1] and an accompanying Application Programming Interface, developed for the Application Specific Electronic Module (ASEM) project sponsored by ARPA, are presented as examples of a novel approach to the representation of standards for the ATE industry. Introducti...

Theoretical Background for the Applet-based Exercises: • Test Generation and Fault Diagnosis • Boundary Scan

Boundary-Scan and In-Circuit Test Combined: Strategy and Benefits

Boundary scan components have testability logic built-in which can be used to test for PCB process faults as well as component functionality; therefore, many manufacturers have turned to a boundary scan test strategy to help them solve problem caused by loss of test access. Some have turned to boundary scan only test solutions, but these solutions are limited by the configuration of the boundar...